HC705CT4GRSSLASHD datasheet(55/152 Pages) NXP

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MC68HC705CT4 — Rev. 2.0

General Release Specification

MOTOROLA

Parallel Input/Output (I/O)

General Release Specification — MC68HC705CT4

Section 7. Parallel Input/Output (I/O)

7.1 Contents

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.6

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7.7

Input/Output Port Pin Programming . . . . . . . . . . . . . . . . . . . . .57

7.2 Introduction

In user mode 31 lines are arranged as one 7-bit and three 8-bit ports.

Most of these port pins are programmable as either inputs or outputs

under software control of the data direction registers, though some are

input only.

NOTE:

To avoid a glitch on the output pins, write data to the I/O port data

7.3 Port A

Port A is an 8-bit bidirectional port that does not share any of its pins with

other subsystems. The port A data register is at $0000 and the data

direction register (DDR) is at $0004. Reset does not affect the data

registers, but clears the data direction registers, thereby returning the

ports to inputs. Writing a logic 1 to a DDR bit sets the corresponding port

bit to output mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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