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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HC705CT4GRS/D 데이터시트(PDF) 61 Page - NXP Semiconductors |
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HC705CT4GRS/D 데이터시트(HTML) 61 Page - NXP Semiconductors |
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61 / 152 page  16-Bit Timer Counter Register MC68HC705CT4 — Rev. 2.0 General Release Specification MOTOROLA 16-Bit Timer 61 Figure 8-1. 16-Bit Timer Block Diagram The free-running counter is configured to $FFFC during reset and is a read-only register but only when the timer is enabled. During a power-on reset, the counter is also preset to $FFFC and begins running only after the TON bit in the TIMER control register is set. Because the free- running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled when counter roll-over occurs by setting its interrupt enable bit (TOIE). NOTE: The I bit in the CCR should be set while manipulating both the high and low byte registers of a specific timer function to ensure that an interrupt does not occur. INPUT CAPTURE REGISTER CLOCK INTERNAL BUS OUTPUT COMPARE REGISTER HIGH BYTE LOW BYTE $16 $17 ÷4 INTERNAL PROCESSOR 16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER 8-BIT BUFFER HIGH BYTE LOW BYTE $1A $1B $18 $19 HIGH BYTE LOW BYTE $14 $15 OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT EDGE DETECT CIRCUIT TIMER STATUS REG. ICF OCF TOF $13 ICIE IEDG OLVL OUTPUT LEVEL REG. RESET TIMER CONTROL REG. $12 OUTPUT LEVEL (TCMP) INTERRUPT CIRCUIT TOIE OCIE EDGE INPUT (TCAP) D CLK C Q FOLVL PD6 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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