HC705CT4GRSSLASHD datasheet(62/152 Pages) NXP

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16-Bit Timer

General Release Specification

MC68HC705CT4 — Rev. 2.0

16-Bit Timer

MOTOROLA

8.4 Output Compare Register

The 16-bit output compare register is made up of two 8-bit registers at

locations $16 (MSB) and $17 (LSB). The output compare register is

used for several purposes, such as indicating when a period of time has

elapsed. All bits are readable and writable and are not altered by the

timer hardware or reset. If the compare function is not needed, the two

bytes of the output compare register can be used as storage locations.

The output compare register contents are continually compared with the

contents of the free-running counter. If a match is found, the

corresponding output compare flag (OCF) bit is set and the

corresponding output level (OLVL) bit is clocked to an output level

should be changed after each successful comparison to establish a new

elapsed time-out. An interrupt can also accompany a successful output

compare provided the corresponding interrupt enable bit (OCIE) is set.

After a processor write cycle to the output compare register containing

the MSB ($16), the output compare function is inhibited until the LSB

($17) is also written. The user must write both bytes (locations) if the

MSB is written first. A write made only to the LSB ($17) will not inhibit the

compare function. The free-running counter is updated every four

internal bus clock cycles. The minimum time required to update the

output compare register is a function of the program rather than the

internal hardware.

The processor can write to either byte of the output compare register

without affecting the other byte. The output level (OLVL) bit is clocked to

the output level register regardless of whether the output compare flag

(OCF) is set or clear.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D 데이터시트(PDF) 62 Page - NXP Semiconductors