HC705CT4GRSSLASHD datasheet(64/152 Pages) NXP

64 / 152 page

16-Bit Timer

General Release Specification

MC68HC705CT4 — Rev. 2.0

16-Bit Timer

MOTOROLA

8.6 Timer Control Register

The TCR is a read/write register containing six control bits. Three bits

control interrupts associated with the timer status register flags ICF,

OCF, and TOF.

ICIE — Input Capture Interrupt Enable

1 = Interrupt enabled

0 = Interrupt disabled

OCIE — Output Compare Interrupt Enable

1 = Interrupt enabled

0 = Interrupt disabled

TOIE — Timer Overflow Interrupt Enable

1 = Interrupt enabled

0 = Interrupt disabled

TON — Timer On

When disabled, the timer is initialized to the reset condition.

1 = Timer enabled

0 = Timer disabled

IEDG — Input Edge

Value of input edge determines which level transition on the TCAP pin

will trigger a free-running counter transfer to the input capture

1 = Positive edge

0 = Negative edge

Address:

$0012

Bit 7

654321

Bit 0

Read:

ICIE

OCIE

TOIE

TON

IEDG

OLVL

Write:

Reset:

00000000

Figure 8-2. Timer Control Register (TCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D 데이터시트(PDF) 64 Page - NXP Semiconductors

HC705CT4GRS/D 데이터시트(HTML) 64 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL