HC705CT4GRSSLASHD datasheet(56/152 Pages) NXP

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Parallel Input/Output (I/O)

General Release Specification

MC68HC705CT4 — Rev. 2.0

Parallel Input/Output (I/O)

MOTOROLA

7.4 Port B

Port B is an 8-bit bidirectional port. The port B data register is at $0001

and the data direction register (DDR) is at $0005. Reset does not affect

the data registers, but clears the data direction registers, thereby

returning the ports to inputs. Writing a logic 1 to a DDR bit sets the

corresponding port bit to output mode.

7.5 Port C

Port C is an 8-bit bidirectional port. The port C data register is at $0002

and the data direction register (DDR) is at $0006. Reset does not affect

the data registers, but clears the data direction registers, thereby

returning the ports to inputs. Writing a logic 1 to a DDR bit sets the

corresponding port pin to output mode. Each of the port C pins has an

optional pullup device. When the DDR bit is cleared and the pullup

device is enabled, the pin will be a pullup

and an interrupt pin. The edge-

or edge- and level-sensitivity of the IRQ pin also pertains to the enabled

port C pins. Care needs to be taken when using port C pins that have the

pullup enabled. Before switching from an output to an input, the data

should be preconditioned to a logic 1 to prevent an interrupt from

occurring. Port C bit 7 is also shared with the PWM output. When PC7

is used as the PWM output, its pullup option should not be selected (see

Figure 7-1).

Figure 7-1. Port C Pullup Option

PC7

VDD

DDR BIT

NORMAL PORT CIRCUITRY

AS SHOWN IN FIGURE 7-2

IRQ

SCHMITT

TRIGGER

TO INTERRUPT

LOGIC

MASK OPTION (PC7PU)

DISABLED

ENABLED

(PC7 ADDS PWM)

FROM ALL OTHER PORT C PINS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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