HC705CT4GRSSLASHD datasheet(63/152 Pages) NXP

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16-Bit Timer

Input Capture Register

MC68HC705CT4 — Rev. 2.0

General Release Specification

MOTOROLA

16-Bit Timer

8.5 Input Capture Register

Two 8-bit registers, which make up the 16-bit input capture register, are

read-only and are used to latch the value of the free-running counter

after the corresponding input capture edge detector senses a defined

transition. The level transition that triggers the counter transfer is defined

by the corresponding input edge bit (IEDG). Reset does not affect the

contents of the input capture register.

The result obtained by an input capture is one more than the value of the

free-running counter on the rising edge of the internal bus clock

preceding the external transition. This delay is required for internal

synchronization. Resolution is one count of the free-running counter,

which is four internal bus clock cycles.

The free-running counter contents are transferred to the input capture

capture flag (ICF) is set or clear. The input capture register always

contains the free-running counter value that corresponds to the most

recent input capture.

After a read of the input capture register MSB ($14), the counter transfer

is inhibited until the LSB ($15) is also read. This characteristic causes

the time used in the input capture software routine and its interaction

with the main program to determine the minimum pulse period. A read

of the input capture register LSB ($15) does not inhibit the free-running

counter transfer since they occur on opposite edges of the internal bus

clock.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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