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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HC705CT4GRS/D 데이터시트(PDF) 86 Page - NXP Semiconductors |
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HC705CT4GRS/D 데이터시트(HTML) 86 Page - NXP Semiconductors |
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86 / 152 page  Dual Phase-Locked Loop (PLL) General Release Specification MC68HC705CT4 — Rev. 2.0 86 Dual Phase-Locked Loop (PLL) MOTOROLA 11.2 Introduction This dual PLL is similar to that of the MC145162 60-MHz universal programmable dual PLL frequency synthesizer. It is especially designed for CT-1 cordless phone applications. The PLL features fully programmable 16-bit receive, 16-bit transmit, and 12-bit reference ripple down counters. It also has two independent phase detectors for transmit and receive loops. The FinTx and FinRx signals are input to the PLL transmit and receive counters, respectively. They are typically driven by the loop VCO and AC-coupled. The minimum input signal level is 200 mVp-p @ 60.0 MHz. Figure 11-1. Dual PLL Block Diagram OSC 12-BIT PROGRAMMABLE REFERENCE COUNTER ÷ 4 ÷ 5 TxPDOUT RxPDOUT 16-BIT PROGRAMMABLE TX COUNTER 16-BIT PROGRAMMABLE RX COUNTER FinT FinR PLS1 PLS0 MCU BUS (10.24 MHz) ÷ 25 TX PHASE DETECTOR RX PHASE DETECTOR Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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