HC705CT4GRSSLASHD datasheet(83/152 Pages) NXP

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Core Timer

Core Timer Counter Register

MC68HC705CT4 — Rev. 2.0

General Release Specification

MOTOROLA

Core Timer

10.4 Core Timer Counter Register

The timer counter register is a read-only register that contains the

current value of the 8-bit ripple counter at the beginning of the timer

chain. This counter is clocked by the CPU clock (E/4) and can be used

for various functions including a software input capture. Extended time

periods can be attained using the TOF function to increment a temporary

RAM storage location, thereby simulating a 16-bit (or more) counter.

The power-on cycle clears the entire counter chain and begins clocking

the counter. After 4064 cycles, the power-on reset circuit is released,

which again clears the counter chain and allows the device to come out

of reset. At this point, if RESET is not asserted, the timer starts counting

up from zero and normal device operation begins. When RESET is

asserted any time during operation (other than POR), the counter chain

is cleared.

Address

$0009

Bit 7

654321

Bit 0

Read:

Write:

Reset:

00000011

= Unimplemented

Figure 10-3. Core Counter Register (CTCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D 데이터시트(PDF) 83 Page - NXP Semiconductors