HC705CT4GRSSLASHD datasheet(89/152 Pages) NXP

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Dual Phase-Locked Loop (PLL)

Registers

MC68HC705CT4 — Rev. 2.0

General Release Specification

MOTOROLA

Dual Phase-Locked Loop (PLL)

11.3.2 12-Bit Reference Counter Modulus Register

This 2-byte register holds the count for the 12-bit reference counter. The

reference counter is shut off and held in reset when the REFON bit is

cleared. For proper operation, this register must not be loaded with a

value less than $000F.

NOTE:

Bit 4 to bit 7 of $000B are not used but they are physically present. The

user may use these four bits for scratch memory.

Address:

$000B

Bit 7

654321

Bit 0

Read:

PLLRC11 PLLRC10

PLLRC9

PLLRC8

Write:

Reset:

00000000

Address:

$000C

Bit 7

654321

Bit 0

Read:

PLLRC7

PLLRC6

PLLRC5

PLLRC4

PLLRC3

PLLRC2

PLLRC1

PLLRC0

Write:

Reset:

00000000

= Unimplemented

Figure 11-3. 12-Bit Reference Counter (PLLRC)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D 데이터시트(PDF) 89 Page - NXP Semiconductors

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