HC705CT4GRSSLASHD datasheet(81/152 Pages) NXP

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Core Timer

Core Timer Control and Status Register

MC68HC705CT4 — Rev. 2.0

General Release Specification

MOTOROLA

Core Timer

10.3 Core Timer Control and Status Register

The CTCSR contains the timer interrupt flag, the timer interrupt enable

bits, and the real time interrupt rate select bits. Figure 10-2 shows the

value of each bit in the CTCSR when coming out of reset.

CTOF — Core Timer Overflow

CTOF is a read-only status bit set when the 8-bit ripple counter rolls

over from $FF to $00. Clearing CTOF is done by writing a logic 1 to

TOFC. Writing to CTOF has no effect. Reset clears CTOF.

RTIF — Real Time Interrupt Flag

The real-time interrupt circuit consists of a 3-stage divider and a one-

of-four selector. The clock frequency that drives the RTI circuit is

E/2**14 (or E/16,384) with three additional divider stages, giving a

maximum interrupt period of 64 milliseconds at a bus rate of 2.048

MHz. RTIF is a clearable, read-only status bit and is set when the

output of the chosen (one-of-four selection) stage goes active.

Clearing RTIF is done by writing a logic 1 to RTFC. Writing to RTIF

has no effect. Reset clears RTIF.

TOFE — Timer Overflow Enable

When this bit is set, a CPU interrupt request is generated when the

CTOF bit is set. Reset clears this bit.

RTIE — Real-Time Interrupt Enable

When this bit is set, a CPU interrupt request is generated when the

RTIF bit is set. Reset clears this bit.

Address

$0008

Bit 7

654321

Bit 0

Read:

CTOF

RTIF

TOFE

RTIE

RT1

RT0

Write:

TOFC

RTRC

Reset:

00000011

= Unimplemented

Figure 10-2. Core Timer Control and Status Register (CTCSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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