TIR2000 datasheet(39/63 Pages) TI

39 / 63 page

4–3

MIR/FIR (DMA) Mode

Bit No

Definition

Not

used

DMA

asserted

underrun

Status

FIFO

threshold

Not

used

Status FIFO

time-out

Not used

Default

Bit definition:

BIT NO.

DESCRIPTIONS

Not used

Status FIFO time-out interrupt pending. Bit 2 is cleared to 0 by reading the Status FIFO.

Not used

Status FIFO threshold interrupt pending. Bit 4 is cleared to 0 by reading the Status FIFO.

Transmit underrun pending. Bit 5 is set to a 1 when an underrun occurs in the data transmit FIFO. Bit 5 is

cleared to 0 by servicing the underrun.

DMA terminal count occurred interrupt pending. In the DMA mode, bit 6 is set to 1 when the terminal count

(TC) is asserted. Bit 6 is cleared to 0 by reading the Status FIFO.

Not used

TV Mode

IIR_TV

Bit No

Definition

underrun

error

RX FIFO

overrun error

TX FIFO

below

threshold

RX FIFO

over

threshold

Default

Bit definition:

BIT NO.

DESCRIPTIONS

Receiver interrupt pending. Bit 0 is set to a 1 when the receiver FIFO level is equal to or above its threshold

level.

Transmitter interrupt pending. Bit 1 is set to a one when the transmitter FIFO level is below its threshold level.

always 0

Receiver FIFO overrun interrupt. Bit 3 is set to a one when an overrun occurs in the data RX FIFO.

always 0

Transmit underrun interrupt pending. Bit 5 is set to a one when an underrun occurs in the data transmit FIFO.

always 0

TIR2000 데이터시트(PDF) 39 Page - Texas Instruments

TIR2000 데이터시트(HTML) 39 Page - Texas Instruments

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