TIR2000 datasheet(18/63 Pages) TI

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2–6

Program the interrupt configuration register (ICR) in order to:

•

Select the IRQ channel

•

Select either totem-pole or open-drain output

•

Select an active high or an active low for an interrupt when the totem-pole configuration is

selected.

In the MIR mode, the 48-MHz input clock is automatically divided by 1.5 to generate the 28x MIR

clock. However, a 6 should be written to the PRES register which is used as the base clock for

the status FIFO timeout interrupt.

2.1.2.1

MIR-Data Transmission Mode

The following register programming steps are performed for transmission in the MIR mode:

Program the mode-definition register (MDR) to:

•

Select the MIR mode

•

Enable/disable the low-power mode. The low-power mode is enabled for normal operation.

•

Enable/disable the sleep mode. The sleep mode is disabled for normal operation.

•

Enable/disable the store and controlled transmission. The SCT is disabled for normal

operation.

•

Enable/disable the software control on the 1.6-

µs infrared pulse. The software control is

disabled during normal operation.

•

Select the frame closing method (frame-length method or set–EOT bit method)

Program the PLR to:

•

Select the number of Start Flags. The default value is two.

•

Select the TX FIFO trigger level.

When the frame-length method is selected for frame closing, program the TXFLL and the TXFLH

registers for the frame length.

Reset the TX FIFO:

•

Write the LCR register so that the LCR[7] bit is a 1. The LCR[7] bit must be a 1 in order to write

to the FCR[5] bit.

•

Program the FCR to select 64-/16-bytes of TX FIFO, non-DMA/DMA mode of operation , and

to clear the TX FIFO.

•

Write the LCR register so that the LCR[7] bit is a 0 for normal operation.

Program the IER register to enable only the transmission related interrupts and disable the

remaining interrupts. The TX threshold interrupt and the TX underrun interrupt are enabled.

Write a 1 to the ACREG[7] bit to enable data transmission.

Write a 1 to the MCR[3] bit to enable the selected IRQ channel.

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