TIR2000 datasheet(49/63 Pages) TI

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4–13

4.13 Bank 2 Registers

4.13.1

Prescaler Register (PRESC)

Address: A (Hex) – Bank 2

Bit No.

[7–6]

[5–0]

Description

Not used

Prescaler Value

Default

011010

Bits[5–0]: Prescaler Value. The prescaler unit divides the 48-MHz input clock by the value in the PRESC

clock. The default value for the PRESC register is 1A(Hex).

4.13.2

Interrupt Configuration Register (ICR) – (write only)

Address: B (Hex) – Bank 2

Bit No.

[5–4]

[3–0]

Description

IRQ active level select

IRQ output mode

select

Status FIFO threshold

level

IRQ channel select

Default

0001

Bits [3–0]: IRQ channel select. There are 11 IRQ channels. Any particular IRQ channel can be selected by

programming the ICR[3–0] bits.

ICR[3–0]

IRQ channel

ICR[3–0]

IRQ channel

0001

IRQ3

0111

IRQ10

0010

IRQ4

1000

IRQ11

0011

IRQ5

1001

IRQ12

0100

IRQ6

1010

IRQ14

0101

IRQ7

1011

IRQ15

0110

IRQ9

Others

None

Bits [5–4]: These two bits decide the threshold level needed:

BIT [5–4]

THRESHOLD LEVEL

Bit 6: IRQ output mode select. IRQ output can be a totem-pole or an open-drain output. A 0 on bit 6 selects

the open-drain output and a 1 selects the totem-pole output. The default value is 0 (open drain). In the

totem-pole output configuration, the output can be a 1, a 0 or a Z, whereas in the open-drain configuration,

the output can be only a 0 or a Z.

Bit 7: In the totem-pole configuration. IRQ output can be an active high or an active low. When the IRQ[7]

bit is a 0, active high is selected and when the IRQ[7] bit is a 1, active low is selected. The default value is

a 0 (active high). Bit 7 is not relevant when open drain is selected.

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