TIR2000 datasheet(33/63 Pages) TI

33 / 63 page

3–3

3.5

FIFO-Control Register (FCR) – (write only)

Address: 2 (Hex)

Bit definitions:

BIT NO.

DEFAULT

DESCRIPTIONS

FIFO enable. When set to 1, bit 0 enables both the transmitter and receiver FIFOs. Bit 0

must be 1 when setting other FCR bits. Changing bit 0 clears the FIFO registers.

Receiver FIFO reset. When set to 1, bit 1 clears all bytes in the receiver FIFO and resets

its counter to 0. The shift register is not cleared. A logic 1 written to this bit is self clearing.

Transmitter FIFO reset. When set to 1, bit 2 clears all types in the transmitter FIFO and

resets the counter to 0. The shift register is not cleared. A logic 1 written to bit 2 is self

clearing.

DMA mode select. Set to 1 to enable DMA or 0 to disable DMA.

Reserved

FIFO size selection. When set to 1, 64-byte mode is selected. When set to 0, 16-byte mode

is selected. A write instruction to FCR5 is ignored when line-control register (LCR[7]) is 0.

LCR[7] needs to be a 0 for normal operation.

Receiver FIFO trigger level selection (LSB)

Receiver FIFO trigger level selection (MSB)

Bit 6 and Bit 7 trigger levels are as follows:

BIT 7

BIT 6

16-BYTE RECEIVER FIFO TRIGGER

LEVEL (BYTES)

64-BYTE RECEIVER FIFO TRIGGER

LEVEL (BYTES)

3.6

Line Control Register (LCR) - (read and write)

Address: 3 (Hex)

Bit definitions:

BIT NO.

DEFAULT

DESCRIPTION

Word length select bit 0 (WLS0)

Word length select bit 1 (WLS1)

Bits 0 and bit 1 specify the number of bits in each transmitted or received serial character.

BIT 1

BIT 0

WORD LENGTH

5 bits

6 bits

7 bits

8 bits

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