TIR2000 datasheet(35/63 Pages) TI

35 / 63 page

3–5

3.8

Line Status Register (LSR) - (read only)

Address: 5 (Hex)

Bit Definitions:

BIT NO.

DESCRIPTION

Data-ready (DR) indicator for the receiver. Bit 0 is set to a 1 when a complete incoming character is

received and transferred into the receiver buffer register or the FIFO. Bit 0 is reset to 0 by reading all of

the data in the receiver buffer register or the FIFO register.

Overrun-error (OE) indicator. When bit 1 is set to a 1, it indicates that before the character in the receiver

buffer register was read, it was overwritten by the next character transferred into the register. Bit 1 is reset

every time the CPU reads the contents of the line-status register. When the FIFO-mode data continues

to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full and the next

character has been completely received in the shift register.

Parity-error (PE) indicator. When bit 2 is set to 1, it indicates that the parity of the received data character

does not match the parity selected in the line-control register (bit 4). Bit 2 is reset every time the CPU reads

the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it

applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.

Framing-error indicator. When bit 3 is set to a 1, it indicates that the received character does not have

a valid (1) stop bit. Bit 3 is reset every time the CPU read the contents of the LSR. In the FIFO mode, this

error is associated with the particular character in the FIFO to which it applies. This error is revealed to

the CPU when its associated character is at the top of the FIFO. The UART tries to re-synchronize after

an framing error (FE). To accomplish this, it is assumed that a FE is caused by the next start bit. The UART

samples this start bit twice and then accepts the input data.

Break-interrupt (BI) indicator. When bit 4 is set to a 1, it indicates that the received data input was held

low for longer than a full-word transmission time. A full-word transmission time is defined as the total time

to transmit the start, data, parity, and stop bits. Bit 4 is reset every time the CPU reads the contents of

the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it

applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When

a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after

SIN goes to the marking state for at least two RCLK samples and then receives the next valid start bit.

Transmitter holding register empty (THRE) indicator. Bit 5 is set to 1 when the transmitter holding register

is empty, indicating that the UART is ready to accept a new character. If the THRE interrupt is enabled

when bit 5 is a 1, an interrupt is generated. Bit 5 is set to 0 when the contents of the transmitter holding

the transmitter holding register by the CPU. In the FIFO mode, bit 5 is set when the transmit FIFO is empty;

it is cleared when at least one byte is written to the transmit FIFO.

Transmitter empty (TEMT) indicator. Bit 6 is set to 1 when the transmitter holding register and the

transmitter shift register are both empty. In the FIFO mode, bit 6 is set to 1 when the transmitter FIFO and

shift register are both empty.

Error in receiver FIFO (ER_RCV_FIFO). Bit 7 is set to a 1 if there is at least 1 framing-error, parity-error

or break-indication in the receiver FIFO. If the FIFO is disabled, this bit is always 0. Bit 7 is cleared when

the CPU reads the LSR if there are no other errors in the receiver FIFO.

TIR2000 데이터시트(PDF) 35 Page - Texas Instruments

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