TIR2000 datasheet(43/63 Pages) TI

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4–7

4.9.1

Sleep Mode

When the MDR[3] bit is a 1 and other conditions are satisfied, the device goes into the sleep mode. In sleep

mode the oscillator is shut off and there is no clock running inside the TIR2000. This feature is useful for

saving power consumption. The scope of sleep mode depends on the mode of operation as listed below:

UART mode: The device is always awake when there is a byte in the transmitter, activity on SIN, or when

the device is in the loopback mode. The device is also awake when either delta-CTS, delta-DSR, delta-DCD,

or TERI = 1.

MIR mode: Sleep mode is applicable only during data transmission. The CPU must disable the sleep mode

during data reception by writing a 0 to the MDR[3] bit. When the transmitting peripheral device is idle and

the transmitter FIFO is empty the device goes into the sleep mode. When the CPU writes data to the TX

FIFO register the oscillator is turned on and the clock becomes alive. However it takes 1ms for the oscillator

to be stable and the clock to be valid.

FIR mode: Sleep mode is applicable both during data transmission and data reception. The device goes

into the sleep mode when the transmitting peripheral device is idle, the TX FIFO register is empty and the

receiver is also idle. The clock becomes alive when the CPU writes data to the TX FIFO register or the

receiver starts receiving data. However, it takes 1ms for the oscillator to be stable and the clock to be valid.

SIR and SHARP IR mode: The scope is similar to UART mode and operates for both data transmission and

data receive.

TV mode: Sleep mode is applicable for both data transmission and data receive.

4.9.2

Low-Power Mode

The mechanism of low-power mode is the same as the sleep mode except that the low-power mode is

controlled by the MDR[4] bit and the oscillator keeps running. In low-power mode, the oscillator is not shut

off; only the clock inside the device is disabled. In sleep mode it takes 1 ms to change from sleep mode to

normal mode, whereas the device can change from low-power mode to normal mode immediately.

4.10 Configuration Control Register (CCR) – (write only)

Address 9 (Hex)

CCR

Bit No.

[7–6]

[5–0]

Description

BANK SELECT

Not used

Default

There are four register banks with addresses from A to F. To write to/read from a register in any bank, the

corresponding bank must be selected by writing to the CCR bits[7–6].

BITS CCR[7–6]

BANK SELECTION

Bank 0

Bank 1

Bank 2

Bank 3

4.11 BANK 0 REGISTERS

4.11.1

Transmit Frame-Length Register Low (TXFLL) – (write only)

Address: A (Hex) – Bank 0

Bit No.

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

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