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TIR2000 데이터시트(PDF) 14 Page - Texas Instruments

부품명 TIR2000
상세설명  High-Speed Serial Infrared Controller With 64-Byte FIFO
PDF  63 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

TIR2000 데이터시트(HTML) 14 Page - Texas Instruments

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2–2
2.1.1
Fast-Speed Infrared (FIR) mode
(IrDA 1.1)
During the FIR mode, data transfer takes place between the CPU and peripheral devices at the baud-rate
speed of 4 Mbps. An FIR transmit frame starts with the Preamble, followed by a Start Flag, Frame Data,
CRC-32, and Stop Flag. The details of the frame format can be found in the Infrared Data Association (IrDA)
document physical layer link specification
Preamble
Start Flag
Frame Data
CRC-32
Stop Flag
The peripheral device that is in the data-transmission mode attaches the Preamble, Start Flag, CRC-32, and
the Stop Flag. It also encodes the transmit data into the 4PPM format. During data receive, the peripheral
device in the data-receive mode recovers the data-receive clock, removes the Start Flag, decodes the
4PPM incoming data and determines the frame boundary with the reception of a Stop Flag. It also checks
for errors such as illegal pulse-position-modulation (4PPM) symbols, cyclic reduncy check (CRC) errors and
frame-length errors. At the end of a frame reception, the CPU reads the LSR-status register to find the errors,
if any, of the received frame.
Data cannot be transmitted and received by the same device at the same time. When the CPU wants to send
data, the peripheral device needs to be programmed for data transmission. When the CPU receives data
from the peripheral device, the peripheral device needs to be programmed for data receive. Some registers
are common to both data transmit and data receive and need to be programmed only once. Use the following
programming sequence for these registers:
1.
Program the interrupt configuration register (ICR) in order to:
•
Select the IRQ channel
•
Select either totem-pole or open-drain output
•
Select an active high or an active low for an interrupt when the totem-pole configuration is
selected.
2.
Write a 6 to the PRESC register. This divides a 48-MHz input clock by 6 and generates a 8-MHz
internal clock for the FIR mode of operation.
2.1.1.1
FIR Data-Transmission Mode
The following register programming steps should be performed for transmission in the FIR mode:
1.
Program the mode definition register (MDR) in order to :
•
Select the FIR mode
•
Enable/disable the low-power mode. For normal operation, enable the low-power mode.
•
Enable/disable the sleep mode. For normal operation, disable the sleep mode.
•
Enable/disable the store-and-controlled transmission (SCT). For normal operation, disable
the SCT.
•
Enable/disable the software control on a 2-
µs infrared pulse. For normal operation, disable
the software control.
•
Select the frame closing method (frame-length method or set-EOT bit method).
2.
Program the preamble length register (PLR) in order to:
•
Select the number of preambles. The default value is 16.
•
Select the TX FIFO trigger level
3.
When the frame-length method is selected for frame termination, program the TXFLL and the
TXFLH registers for the frame length value.



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