TIR2000 datasheet(17/63 Pages) TI

17 / 63 page

2–5

Write a 1 to the ACREG[6] to enable data receive.

Write a 1 to the MCR[3] bit. This enables the selected IRQ channel.

This completes the programming of the registers for data receive and now the device is ready to receive

data. The device decodes the serial data, converts it from serial data to parallel data and stores the data

bytes in the RX FIFO. When the stored data in the RX FIFO reaches the set threshold level, the device

interrupts the CPU. When the CPU is interrupted, it reads the IIR to identify the source of the interrupt. When

the source of the interrupt is the IIR[0] bit and not the IIR[7] bit, the CPU goes to the threshold mode.

2.1.1.2.1

Threshold Mode

During threshold mode, the CPU reads a number of bytes (determined by the RX FIFO threshold level) from

the RX FIFO. An example: When the RX threshold value is set to be 16, the CPU can perform 16 consecutive

read operations from the RX FIFO. When the source of interrupts is the IIR[7] bit, the CPU goes to the byte

mode.

2.1.1.2.2

Byte Mode

The CPU will read the majority of the frame in the threshold mode. However, the last bits of data may not

fall on the exact threshold boundary and will not be able to interrupt the CPU with the IIR[0] bit. The device

interrupts the CPU with the IIR[7] bit when the machine in the data-receive mode detects the end of a frame.

The CPU disables the IER[0] bit and reads one byte from the RX FIFO each time and checks for the interrupt

(IIR[2]) bit. When the CPU reads the last byte of a frame from the RX FIFO, the device interrupts the CPU

with the IIR[2] bit. Once the CPU receives the IIR[2] bit, it should not read further from the RX FIFO and that

is the end of the frame. The last four bytes that the CPU read from the RX FIFO are the CRC value and not

the actual data. The CPU enables the IER[0] bit. After the CPU reads the last byte of a frame from the RX

FIFO, it reads the LSR register to determine the sources or errors, if any, for that frame. When the source

of the interrupt is the IIR[3] bit, there has been an overrun while receiving data and the CPU will service the

overrun.

2.1.1.2.3

Data-Receive Overrun

An overrun occurs during data receive if the CPU cannot timely read out data from the RX FIFO and the RX

FIFO is overwritten. When an overrun occurs, the device interrupts the CPU with the IIR[3] bit and discards

the remaining portion of the frame. When an overrun occurs, the device sets an internal flag and the receive

operation of the next frame is disabled. Before the next frame can be received, the CPU must reset the RX

FIFO and read the RESUME register. This read operation clears the internal flag.

2.1.2

Medium-Speed Infrared (MIR) mode (IrDA 1.1)

During the medium speed infrared (MIR) mode, data transfer takes place between the CPU and peripheral

devices at a speed of 1.15 Mbs. A MIR transmit frame starts with a minimum of two Start Flags followed by

the Frame Data, CRC–16 and ends with a Stop Flag.

Start Flag

Frame Data

CRC-16

Stop Flag

The peripheral device in the data transmission mode of operation attaches the Start Flags, CRC-16, and

a Stop Flag. It also looks for five consecutive ones in the frame data and automatically inserts a zero after

five consecutive ones. This operation is known as bit stuffing. On a receive operation, the machine in the

data receive mode recovers the receive clock, removes the Start Flag, de-stuffs the incoming data and

determines frame boundary with the reception of the Stop Flag. It also checks for errors such as frame abort,

CRC error and frame-length error. At the end of a frame reception, the CPU reads the LSR status register

to find out if any errors occurred with the received frame.

The device can both transmit and receive data, but cannot do both at the same time. When the CPU wants

to send data, the perpheral device must be programmed for data transmission. When the CPU receives data

from the peripheral device, the perpheral device must be programmed for data receive. Some registers are

common to both data transmit and data receive and are programmed only once. Use the following

programming sequence for these registers:

TIR2000 데이터시트(PDF) 17 Page - Texas Instruments

TIR2000 데이터시트(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

데이터시트 다운로드

링크 URL