TIR2000 datasheet(45/63 Pages) TI

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4–9

Bit[7–6]: These two bits decide the number of preambles (a fixed pattern of 16 bits) to be transmitted at the

beginning of each frame. The default value of PLR[7–6] = 00 which is equal to 16 preambles.

BIT [7–6]

NO. OF PREAMBLES

4.11.6

Auxiliary Control Register (ACREG) – (read and write)

Address: F (Hex)

Bit No.

Description

enable

Short

time-out

MIR half

mode

Send Ir

pulse

Deferred

TX start

Frame

abort

EOT bit

Default

Bit definition:

BIT NO.

DESCRIPTIONS

End of transmission (EOT) bit. The CPU writes a 1 to bit 0 just before it writes the last byte to the TX FIFO

2.1.1.1.

Frame abort. The CPU can intentionally abort data transmission of a frame by writing a 1 to bit 1. The default

value is a 0. Neither the end flag nor the CRC bits are appended to the frame. The receiver will find the frame

with the abort pattern (1111_111) in the MIR mode and a Phy–error in the FIR mode. The CPU must reset

the TX FIFO and reset the ACREG[1] bit by writing a 0 to bit 1 before next frame can be transmitted.

Store and controlled TX start. When the MDR[5] bit equals to a 1 and the CPU writes a 1 to the ACREG[2]

bit, the transmitting peripheral device starts frame data transmission. Bit 2 is self clearing. See paragraph

2.1.1.2.

Send 2-

µs Ir pulse. When the MDR[6] bit equals to a 1 and the CPU writes a 1 to the ACREG[3] bit, the

transmitting peripheral device sends a 2-

µs IR pulse at the end of the frame. Bit 3 clears automatically by

the transmitting peripheral device at the end of 2-

µs IR pulse data transmission. See paragraph 2.1.1.3.

MIR half mode. When bit 4 is set to a 1, the operating speed in the MIR mode changes to 0.58 Mbs.

Short time-out. When bit 5 is set to a 1, the time-out interval in the Status FIFO time-out interrupt is

changed from 1 ms to 128

µs.

RX enable. Bit 6 must be set to a 1 to enable data receive in all IR modes.

TX enable, Bit 7 must be set to a 1 to enable data transmission in all IR modes.

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