TIR2000 datasheet(44/63 Pages) TI

44 / 63 page

4–8

4.11.2

Transmit Frame-Length Register high (TXFLH) – (write only)

Address: B (Hex) – Bank 0

Bit No.

[7–6]

Description

Not used

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

The TXFLL register along with the TXFLH register stores the value for the number of bytes of a data

transmission frame. The TXFLL register stores the lower 8 bits and the TXFLH register stores the upper bits.

4.11.3

Received Frame-Length Register Low(RXFLL) – (write only)

Address: C (Hex) – Bank 0.

Bit No.

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

4.11.4

Received Frame-Length Register High (RXFLH) – (write only)

Address: D (Hex) – Bank 0.

Bit No.

[7–6]

Description

Not used

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

While receiving data, the maximum length of a frame is limited to the value, written to the RXFLL and the

RXFLH registers. The RXFLL register stores the lower 8 bits and the RXFLH register stores the upper bits.

Any frame greater then the set maximum value will be reported as a frame-length-exceed error. If n is the

intended receive-frame maximum length, then program the (RXFLL, RXFLH) registers to be (n + 3) in the

MIR mode and (n+5) in the FIR mode of operation.

4.11.5

Preamble Length Register (PLR) – (write only)

Address: E (Hex) – Bank 0.

PLR

Bit No.

[7–6]

[5–4]

[3–0]

Description

Preamble length

TX FIFO trigger

Start flags

Default

0010

Bit[3–0]: Number of start flags (relevant only in the MIR mode). The number of start flags to be transmitted

at the beginning of a frame is equal to the PLR[3–0] value. The minimum value is 2.

Bit[5–4]: Data Transmission FIFO trigger level selection or empty space available selection.

BIT [5–4]

16-BYTE RECEIVER FIFO EMPTY

SPACE AVAILABLE (BYTES)

64-BYTE RECEIVER FIFO. EMPTY

SPACE AVAILABLE (BYTES)

Not used

Example: Bit[5–4] are set to 01 and the TX FIFO register is configured for 64 bytes. When the available

empty space in the TX FIFO register increases to 48 bytes, the device interrupts the CPU with the IIR[1]

bit. The CPU can safely write up to 48 bytes to the TX FIFO without the possibility of overwriting the TX FIFO.

TIR2000 데이터시트(PDF) 44 Page - Texas Instruments

TIR2000 데이터시트(HTML) 44 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

데이터시트 다운로드

링크 URL