TIR2000 datasheet(19/63 Pages) TI

19 / 63 page

2–7

When the CPU receives an interrupt, it reads the IIR to identify the source of the interrupt. When the source

of the interrupt is an IIR[1] bit, the CPU requires the following:

•

Disable the IER[1] bit.

•

Write data bytes (maximum number limited to the number selected by the TX FIFO trigger

level) to the TX FIFO.

•

Enable the IER[1] bit.

When the source of the interrupt is the IIR[5] bit, there has been an underrun while transmitting data and

the CPU needs to service the underrun. See paragraph 2.1.1.1.4

2.1.2.2

MIR Data Receive Mode

The following register programming steps are required to receive data in MIR mode:

Program the mode definition register (MDR) in order to:

•

Select the MIR mode

•

Disable the low power mode

•

Disable the sleep mode

Program the RXFLL and RXFLH registers for maximum receive-frame length value. The

maximum length of a frame is 2048 bytes. The RXFLL register stores the lower eight bits and the

RXFLH register stores the remaining upper bits. When the intended maximum receive-frame

length is n, program the RXFLH and RXFLL registers to be n + 3.

Reset the RX FIFO. This includes:

•

Write to the LCR register so that the LCR[7] bit is a 1. LCR[7] bit must be a 1 to be able to write

to the FCR[5] bit.

•

Program the FCR register to select 64-/16- bytes of the RX FIFO, the non-DMA/DMA mode

of operation, select the RX FIFO trigger level and to clear the RX FIFO.

•

Write the LCR register to set the LCR[7] bit to a 0 for normal operation.

Program the IER register to enable only the receive related interrupts and disable the remaining

interrupts. Enable the following:

•

RX threshold interrupt (IER[0] bit)

•

The last byte from the RX FIFO interrupt (IER[2] bit)

•

The RX FIFO overrun interrupt (IER[3] bit)

•

The received end of the frame interrupt (IER[7] bit)

Write a 1 to the ACREG[6] bit to enable data receive.

Write a 1 to the MCR[3] bit to enable the selected IRQ channel.

This completes the programming of the registers for data receive and now the device is ready to receive

data.When the CPU is interrupted, it reads the IIR to identify the source of the interrupt. When the source

of the interrupt is the IIR[7] bit, the CPU goes to the byte mode. See paragragh 2.1.1.2.2. The CRC value

is the last two bytes instead of the last four bytes as in the FIR data-transmission mode.

When the source of the interrupt is the IIR[0] bit and not the IIR[7] bit, the CPU goes into the threshold mode.

See paragraph 2.1.1.2.1. If the source of the interrupt is the IIR[4] bit, there has been an overrun while

receiving data and the CPU will need to service the overrun. See paragraph 2.1.1.2.3.

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