TIR2000 datasheet(38/63 Pages) TI

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4–2

Consumer Remote Mode

Bit definition:

BIT NO.

DEFAULT

DESCRIPTIONS

Received-data-available interrupt enable (1 = enable, 0 = disable). If bit 0 is set, it enables

an interrupt when the receiver FIFO is equal to or above its threshold level.

Transmitter FIFO below threshold level interrupt enable. If bit 1 is set, it enables an interrupt

when the transmitter FIFO is below its threshold level.

write 0

RX FIFO overrun interrupt enable

write 0

Transmitter underrun interrupt enable.

write 0

4.4

Interrupt Identification Register (IIR) – (read only)

Address: 2 (Hex)

MIR/ FIR (Programmed I/O) Mode

IIR_IR

Bit No

Definition

EOF

detected

Not

used

underrun

Not

used

FIFO

overrun

Last byte

read from

FIFO

TX FIFO

below

threshold

RX FIFO

over

threshold

Default

Bit definition:

BIT NO.

DESCRIPTIONS

Receiver interrupt pending. Bit 0 is set to a 1 when the receiver FIFO level is equal to or above its threshold

level.

Transmitter interrupt pending. Bit 1 is set to a 1 when the transmitter FIFO level is below its threshold level.

Bit 2 is set to a 1 when the CPU reads the last byte of a frame from the receiver FIFO. Bit 2 is cleared

when it is read. The CPU uses bit 2 along with bit 7 to locate the end of the frame.

Receiver FIFO overrun interrupt. Bit 3 is set to a 1 when an overrun occurs in the RX FIFO. Overrun occurs

when the CPU cannot read data fast enough from the RX FIFO and there is no empty space available in

the RX FIFO register to store frame data. If an overrun occurs, the CPU

has to service the overrun before the TIR2000 can receive data further.

Not used

Transmit underrun interrupt pending. Bit 5 is set to a 1 when an underrun occurs in transmit FIFO. Bit 5 is

cleared by servicing the underrun.

Not used

Received end-of-frame interrupt pending. Bit 7 is set to a 1 when the receiver detects the last byte of a

frame. This is different from bit 2. Bit 2 is set to a 1 when the CPU reads the last byte of a frame from the

FIFO. Bit 7 is set prior to bit 2. Bit 7 is cleared to a 0 when it is read.

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