TIR2000 datasheet(16/63 Pages) TI

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2–4

2.1.1.1.3

1.6-

µs Infrared (IR)-Pulse Select Method

During the MIR and FIR mode of operation, the transmitter sends a 1.6-

µs pulse at least once every 500

ms. The purpose of this special pulse is to inform the slow device (in SIR mode) that the high-speed device

involved in data transaction is currently occupied. When the MDR[6] bit is a 0 (the default value), the

peripheral device in the transmit mode always sends a 1.6-

µs pulse at the end of a transmission frame.

However, when bit MDR[6] is a 1, the transmission of a 1.6-

µs pulse depends on the ACREG[3] bit value.

The CPU keeps a timer and sets the ACREG[3] bit at least once in every 500 ms. When the MDR[6] bit is

a 1, the peripheral device in the transmit mode sends a 1.6-

µs pulse only if the ACREG[3] bit is a 1. The

advantage to this approach over the default value sent-always-1.6-

µs pulse-at-the-end approach is that the

peripheral device in the transmit mode need not send the special 1.6-

µs pulse at the end of every frame.

Sending a 1.6-

µs pulse at the end of every frame may increase overhead, mainly in the MIR mode.

2.1.1.1.4

Data-Transmission Underrun

An underrun during data transmission occurs when the CPU fails to supply the data to the TX FIFO and the

TX FIFO becomes empty before the end of the frame is transmitted. When an underrun occurs, the device

closes the frame with an end-flag but attaches an incorrect CRC value. The receiving device detects the

CRC error and discards the frame. The device sets an internal flag and further transmission of data is

disabled. The CPU must reset the TX FIFO and read the RESUME register. This read operation clears the

internal flag.

2.1.1.2

FIR Data-Receive Mode

The following register programming steps are required to receive data in FIR mode:

Program the mode definition register (MDR) to:

•

Select the FIR mode

•

Enable the low-power mode

•

Disable the sleep mode

Program the RXFLL and RXFLH registers for the receive-frame length value. The maximum

length of a frame is 2048 bytes. The RXFLL register stores the lower eight bits and the RXFLH

program the RXFLH and RXFLL registers to be n + 5.

Reset the RX FIFO. This includes:

•

Write to the LCR register that the LCR[7] bit is a 1. The LCR[7] bit must be a 1 to be able to

write to the FCR[5] bit.

•

Program the FCR register to select 64-/16-bytes of the RX FIFO, the non-DMA/DMA mode of

operation, select the RX FIFO trigger level and to clear the RX FIFO.

•

Write the LCR register to set the LCR[7] bit to a 0 for normal operation.

Program the IER register to enable only the receive related interrupts and disable the remaining

interrupts. Enable the following:

•

RX threshold interrupt (IER[0] bit)

•

The last byte from the RX FIFO interrupt (IER[2] bit)

•

The RX FIFO overrun interrupt (IER[3] bit)

•

The received end of the frame interrupt (IER[7] bit)

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