TIR2000 datasheet(28/63 Pages) TI

28 / 63 page

2–16

Program the baud-rate divisor lower byte (DLL) register and the baud-rate divisor higher byte

(DLM) register to select the desired communication baud rate for the UART mode. The baud rate

is given by:

IN +

Input clock frequency to the chip

PRESC

+ PRESC register value

Baud Rate

+ Desired baud rate

so the formula for the Divisor is:

Divisor

PRESC

BaudRate

Where

Baud rate

PRESC

Divisor

(5)

The two 8-bit baud-rate divisor registers (DLL and DLM) store the divisor in a 16-bit binary format. The device

can be changed to the UART mode from any other mode of operation by writing to the DLL or the DLM

registers. This changes the MDR register MDR[2–0] bits to the UART mode automatically (known as the

fall-back mechanism). The PRESC register also automatically changes to the default value.

Program the prescaler (PRESC) register so that the prescaler output is approximately 1.843

MHz. For an input frequency of 48 MHz, use the default PRESC value (26).

Program the mode-definition register (MDR) in order to:

•

Select the UART mode.

•

Enable/disable the low-power mode. For normal operation, the low-power mode is enabled.

•

Enable/disable the sleep mode. For normal operation, the sleep mode is disabled.

Program the line-control register (LCR) in order to:

•

Select the word length.

•

Select the number of stop bits.

•

Enable/disable parity generation.

•

Select even/odd parity.

•

Enable/disable stick parity.

•

Enable/disable the break control.

Program the LCR to select the TX FIFO trigger level.

Reset the TX FIFO. This includes the following:

•

Write to the LCR register to set the LCR[7] bit to a 1. The LCR[7] bit must be a 1 in order to be

able to write to the FCR(5) bit.

•

Program the FCR register to select 64-/16-bytes TX FIFO register, non-DMA mode of

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