TIR2000 datasheet(40/63 Pages) TI

40 / 63 page

4–4

4.5

FIFO Control Register (FCR) – (write only)

Address: 2 (Hex)

MIR, FIR And Consumer Mode

Bit definition:

BIT NO.

DEFAULT

DESCRIPTIONS

FIFO enable. When set to 1, Bit 0 enables both the transmitter and the receiver FIFOs. Bit

0 must be a 1 when setting other FCR bits. Changing bit 0 clears the FIFO.

Receiver FIFO reset. When set to 1, bit 1 clears all bytes in the receiver FIFO and resets

its counter to 0. The shift register in the TV mode is not cleared. A 1 written to bit 1 is self

clearing.

Transmitter FIFO reset. When set to 1, bit 2 clears all bytes in the transmitter FIFO and reset

its counter to 0. The shift register in the TV mode is not cleared. A 1 written to bit 2 is self

clearing.

DMA mode select. DMA mode is selected when bit 3 is set to 1.

Not used

When set to 1, 64–byte transmitter and 64–byte receiver FIFO are selected. When set to 0,

the 16–byte transmitter and the 16–byte receiver FIFO are selected. LCR[7] bit must be a

1 in order to write to bit 5. After writing to bit 5, the LCR[7] bit should be changed to a 0.

Receiver FIFO trigger level selection.

Bit 6 and bit 7 trigger levels are as follows:

BIT 7

BIT 6

16–BYTE RECEIVER FIFO

TRIGGER LEVEL (BYTES)

64–BYTE RECEIVER FIFO

TRIGGER LEVEL (BYTES)

TIR2000 데이터시트(PDF) 40 Page - Texas Instruments