DSP56362AD datasheet(43/168 Pages) MOTOROLA

43 / 168 page

Specifications

Internal Clocks

MOTOROLA

DSP56362 Advance Information

2-5

INTERNAL CLOCKS

Table 2-4 Internal Clocks, CLKOUT

Characteristics

Symbol

Expression1, 2

Min

Typ

Max

Internal operation frequency and

CLKOUT with PLL enabled

f—

(Ef

× MF)/

(PDF

× DF)

—

Internal operation frequency and

CLKOUT with PLL disabled

—

Ef/2

—

Internal clock and CLKOUT high

period

• With PLL disabled

—

ETC

—

• With PLL enabled and

≤ 4

0.49

× ETC ×

PDF

× DF/MF

—

0.51

× ETC ×

PDF

× DF/MF

• With PLL enabled and

MF > 4

0.47

× ETC ×

PDF

× DF/MF

—

0.53

× ETC ×

PDF

× DF/MF

Internal clock and CLKOUT low

period

• With PLL disabled

—

ETC

—

• With PLL enabled and

≤ 4

0.49

× ETC ×

PDF

× DF/MF

—

0.51

× ETC ×

PDF

× DF/MF

• With PLL enabled and

MF > 4

0.47

× ETC ×

PDF

× DF/MF

—

0.53

× ETC ×

PDF

× DF/MF

Internal clock and CLKOUT cycle

time with PLL enabled

—

ETC × PDF ×

DF/MF

—

Internal clock and CLKOUT cycle

time with PLL disabled

—2

× ETC

—

Instruction cycle time

ICYC

—TC

—

Notes: 1.

DF = Division Factor

Ef = External frequency

ETC = External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

TC = internal clock cycle

See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion

of the PLL.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56362AD 데이터시트(PDF) 43 Page - Motorola, Inc

DSP56362AD 데이터시트(HTML) 43 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL