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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56362AD 데이터시트(PDF) 61 Page - Motorola, Inc |
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DSP56362AD 데이터시트(HTML) 61 Page - Motorola, Inc |
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61 / 168 page  Specifications External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-23 Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 No. Characteristics Symbol Expression 20 MHz6 30 MHz6 Unit Min Max Min Max 131 Page mode cycle time for two consecutive accesses of the same direction tPC 2 × TC 100.0 — 66.7 — ns Page mode cycle time for mixed (read and write) accesses. 1.25 x Tc 62.5 — 41.7 — 132 CAS assertion to data valid (read) tCAC TC − 7.5 — 42.5 — 25.8 ns 133 Column address valid to data valid (read) tAA 1.5 × TC − 7.5 — 67.5 — 42.5 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 0.75 × TC − 4.0 33.5 — 21.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 2 × TC − 4.0 96.0 — 62.7 — ns 137 CAS assertion pulse width tCAS 0.75 × TC − 4.0 33.5 — 21.0 — ns 138 Last CAS deassertion to RAS deassertion4 tCRP ns • BRW[1:0] = 00 1.75 × TC − 6.0 81.5 — 52.3 — • BRW[1:0] = 01 3.25 × TC − 6.0 156.5 — 102.2 — • BRW[1:0] = 10 4.25 × TC − 6.0 206.5 — 135.5 — • BRW[1:0] = 11 6.25 × TC – 6.0 306.5 — 202.1 — 139 CAS deassertion pulse width tCP 0.5 × TC − 4.0 21.0 — 12.7 — ns 140 Column address valid to CAS assertion tASC 0.5 × TC − 4.0 21.0 — 12.7 — ns 141 CAS assertion to column address not valid tCAH 0.75 × TC − 4.0 33.5 — 21.0 — ns 142 Last column address valid to RAS deassertion tRAL 2 × TC − 4.0 96.0 — 62.7 — ns 143 WR deassertion to CAS assertion tRCS 0.75 × TC − 3.8 33.7 — 21.2 — ns 144 CAS deassertion to WR assertion tRCH 0.25 × TC − 3.7 8.8 — 4.6 — ns 145 CAS assertion to WR deassertion tWCH 0.5 × TC − 4.2 20.8 — 12.5 — ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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