DSP56362AD datasheet(98/168 Pages) MOTOROLA

98 / 168 page

2-60

DSP56362 Advance Information

MOTOROLA

Specifications

Serial Host Interface SPI Protocol Timing

153

SCK edge to data out

not valid

(data out hold time)

Master

/Slave

Bypassed

TC+5

—

Narrow

TC+55

—

Wide

TC+106

116

—

154 SS assertion to data

out valid (CPHA = 0)

Slave

—

TC+33

—

157

First SCK sampling

edge to HREQ output

deassertion

Slave

Bypassed

2.5

×TC+30

—

Narrow

2.5

×TC+120

—

145

Wide

2.5

×TC+217

—

242

158

Last SCK sampling

edge to HREQ output

not deasserted

(CPHA = 1)

Slave

Bypassed

2.5

×TC+30

—

Narrow

2.5

×TC+80

105

—

Wide

2.5

×TC+136

161

—

159

SS deassertion to

HREQ output not

deasserted (CPHA = 0)

Slave

—

2.5

×TC+30

—

160 SS deassertion pulse

width (CPHA = 0)

Slave

—

TC+6

—

161 HREQ in assertion to

first SCK edge

Master

Bypassed

0.5

× tSPICC +

2.5

×TC+43

121

—

Narrow

0.5

×tSPICC +

2.5

×TC+43

174

—

Wide

0.5

×tSPICC +

2.5

×TC+43

209

—

162

HREQ in deassertion

to last SCK sampling

edge (HREQ in set-up

time) (CPHA = 1)

Master

—

163

First SCK edge to

HREQ in not asserted

(HREQ in hold time)

Master

—

Note:

Periodically sampled, not 100% tested

Table 2-21 Serial Host Interface SPI Protocol Timing (Continued)

No.

Characteristics

Mode

Filter

Mode

Expression

100MHz

Unit

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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