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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56362AD 데이터시트(PDF) 73 Page - Motorola, Inc |
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DSP56362AD 데이터시트(HTML) 73 Page - Motorola, Inc |
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73 / 168 page  Specifications External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-35 Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 No. Characteristics4 Symbol Expression3 80 MHz Unit Min Max 157 Random read or write cycle time tRC 9 × TC 112. 5 —ns 158 RAS assertion to data valid (read) tRAC 4.75 × TC − 6.5 52.9 ns 159 CAS assertion to data valid (read) tCAC 2.25 × TC − 6.5 — 21.6 ns 160 Column address valid to data valid (read) tAA 3 × TC − 6.5 — 31.0 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 162 RAS deassertion to RAS assertion tRP 3.25 × TC − 4.0 36.6 — ns 163 RAS assertion pulse width tRAS 5.75 × TC − 4.0 67.9 — ns 164 CAS assertion to RAS deassertion tRSH 3.25 × TC − 4.0 36.6 — ns 165 RAS assertion to CAS deassertion tCSH 4.75 × TC − 4.0 55.4 — ns 166 CAS assertion pulse width tCAS 2.25 × TC − 4.0 24.1 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × TC ± 2 29.3 33.3 ns 168 RAS assertion to column address valid tRAD 1.75 × TC ± 2 19.9 23.9 ns 169 CAS deassertion to RAS assertion tCRP 4.25 × TC − 4.0 49.1 — ns 170 CAS deassertion pulse width tCP 2.75 × TC − 4.0 30.4 — ns 171 Row address valid to RAS assertion tASR 3.25 × TC − 4.0 36.6 — ns 172 RAS assertion to row address not valid tRAH 1.75 × TC − 4.0 17.9 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 5.4 — ns 174 CAS assertion to column address not valid tCAH 3.25 × TC − 4.0 36.6 — ns 175 RAS assertion to column address not valid tAR 5.75 × TC − 4.0 67.9 — ns 176 Column address valid to RAS deassertion tRAL 4 × TC − 4.0 46.0 — ns 177 WR deassertion to CAS assertion tRCS 2 × TC − 3.8 21.2 — ns 178 CAS deassertion to WR5 assertion tRCH 1.25 × TC − 3.7 11.9 — ns 179 RAS deassertion to WR5 assertion tRRH 0.25 × TC − 3.0 0.1 — ns 180 CAS assertion to WR deassertion tWCH 3 × TC − 4.2 33.3 — ns 181 RAS assertion to WR deassertion tWCR 5.5 × TC − 4.2 64.6 — ns 182 WR assertion pulse width tWP 8.5 × TC − 4.5 101. 8 —ns 183 WR assertion to RAS deassertion tRWL 8.75 × TC − 4.3 105. 1 —ns 184 WR assertion to CAS deassertion tCWL 7.75 × TC − 4.3 92.6 — ns 185 Data valid to CAS assertion (write) tDS 4.75 × TC − 4.0 55.4 — ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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