DSP56362AD datasheet(47/168 Pages) MOTOROLA

47 / 168 page

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56362 Advance Information

2-9

Delay from asynchronous

RESET deassertion to first

external address output

(internal reset deassertion)5

• Minimum

3.25

× TC + 2.0

34.5

—

29.1

• Maximum

20.25 TC + 7.50

—

211.5

176.2

Synchronous reset setup time

from RESET deassertion to

CLKOUT Transition 1

•Minimum

5.9

—

• Maximum

—

10.0

Synchronous reset deasserted,

delay time from the CLKOUT

Transition 1 to the first external

address output

• Minimum

3.25

× TC + 2.0

33.5

—

• Maximum

20.25 TC + 7.5

—

207.5

13 Mode select setup time

30.0

—

30.0

14 Mode select hold time

0.0

—

0.0

Minimum edge-triggered

interrupt request assertion

width

6.6

—

5.5

Minimum edge-triggered

interrupt request deassertion

width

6.6

—

5.5

Delay from IRQA, IRQB, IRQC,

IRQD, NMI assertion to

external memory access

address out valid

• Caused by first interrupt

instruction fetch

4.25

× TC + 2.0

44.5

—

37.4

• Caused by first interrupt

instruction execution

7.25

× TC + 2.0

74.5

—

62.4

Delay from IRQA, IRQB, IRQC,

IRQD, NMI assertion to

general-purpose transfer output

valid caused by first interrupt

instruction execution

× TC + 5.0

105.0

—

88.3

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values6

No.

Characteristics

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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