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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56362AD 데이터시트(PDF) 97 Page - Motorola, Inc |
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DSP56362AD 데이터시트(HTML) 97 Page - Motorola, Inc |
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97 / 168 page  Specifications Serial Host Interface SPI Protocol Timing MOTOROLA DSP56362 Advance Information 2-59 142 Serial clock high period Master Bypassed 0.5 ×tSPICC –10 43 — ns Narrow 0.5 ×tSPICC –10 96 — Wide 0.5 ×tSPICC –10 131 — Slave Bypassed 2.5 ×TC+12 37 — Narrow 2.5 ×TC+102 127 — Wide 2.5 ×TC+189 214 — 143 Serial clock low period Master Bypassed 0.5 ×tSPICC –10 43 — ns Narrow 0.5 ×tSPICC –10 96 — Wide 0.5 ×tSPICC –10 131 — Slave Bypassed 2.5 ×TC+12 37 — Narrow 2.5 ×TC+102 127 — Wide 2.5 ×TC+189 214 — 144 Serial clock rise/fall time Master — — — 10 ns Slave — — — 2000 146 SS assertion to first SCK edge CPHA = 0 Slave Bypassed 3.5 ×TC+15 50 — ns Narrow 0 0 — Wide 0 0 — CPHA = 1 Slave Bypassed 10 10 — Narrow 0 0 — Wide 0 0 — 147 Last SCK edge to SS not asserted slave Bypassed 12 12 — ns Narrow 102 102 — Wide 189 189 — 148 Data input valid to SCK edge (data input set-up time) Master /Slave Bypassed 0 0 — ns Narrow MAX{(20-TC), 0} 10 — Wide MAX{(40-TC), 0} 30 — 149 SCK last sampling edge to data input not valid Master /Slave Bypassed 2.5 ×TC+10 35 — ns Narrow 2.5 ×TC+30 55 — Wide 2.5 ×TC+50 75 — 150 SS assertion to data out active Slave — 2 2 — ns 151 SS deassertion to data high impedance Slave — 9 — 9 ns 152 SCK edge to data out valid (data out delay time) Master /Slave Bypassed 2 ×TC+33 — 53 ns Narrow 2 ×TC+123 — 143 Wide 2 ×TC+210 — 230 Table 2-21 Serial Host Interface SPI Protocol Timing (Continued) No. Characteristics Mode Filter Mode Expression 100MHz Unit Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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