DSP56362AD datasheet(58/168 Pages) MOTOROLA

58 / 168 page

2-20

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

113 RD deassertion

time

100 MHz

0.75

× TC − 4.0

≤ WS ≤ 3]

3.5

—

2.2

—

1.75

× TC − 4.0

≤ WS ≤ 7]

13.5

—

10.6

—

2.75

× TC − 4.0

[WS

≥ 8]

23.5

—

18.9

—

114 WR deassertion

time

100 MHz

0.5

× TC − 4.0

[WS = 1]

1.0

—

0.2

—

TC − 2.0

≤ WS ≤ 3]

6.0

—

6.3

—

2.5

× TC − 4.0

≤ WS ≤ 7]

21.0

—

16.8

—

3.5

× TC − 4.0

[WS

≥ 8]

31.0

—

25.2

—

115 Address valid to

RD assertion

100 MHz

0.5

× TC − 4.0

1.0

—

0.2

—

116 RD assertion pulse

width

100 MHz

(WS + 0.25)

× TC −4.0

8.5

—

6.4

—

117 RD deassertion to

address not valid

100 MHz

0.25

× TC − 2.0

≤ WS ≤ 3]

0.5

—

0.1

—

1.25

× TC − 2.0

≤ WS ≤ 7]

10.5

—

8.4

—

2.25

× TC − 2.0

[WS

≥ 8]

20.5

—

16.7

—

118

TA setup before

RD or WR

deassertion4

0.25

× TC + 2.0

4.5

—

4.1

—

119 TA hold after RD or

WR deassertion

—

0.0

—

Notes:

WS is the number of wait states specified in the BCR.

Timings 100, 107 are guaranteed by design, not tested.

All timings for 100 MHz are measured from 0.5

· Vcc to .05 · Vcc

In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to

remain active

Timing 110, 111, and 112, are not specified for 100 MHz.

Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz3 (Continued)

No.

Characteristics

Symbol

Expression1

100 MHz

120 MHz

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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