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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56362AD 데이터시트(PDF) 77 Page - Motorola, Inc |
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DSP56362AD 데이터시트(HTML) 77 Page - Motorola, Inc |
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77 / 168 page  Specifications External Memory Expansion Port (Port A) MOTOROLA DSP56362 Advance Information 2-39 172 RAS assertion to row address not valid tRAH 2.75 × TC − 4.0 23.5 — 18.9 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 3.5 — 2.2 — ns 174 CAS assertion to column address not valid tCAH 6.25 × TC − 4.0 58.5 — 48.1 — ns 175 RAS assertion to column address not valid tAR 9.75 × TC − 4.0 93.5 — 77.2 — ns 176 Column address valid to RAS deassertion tRAL 7 × TC − 4.0 66.0 — 54.3 — ns 177 WR deassertion to CAS assertion tRCS 5 × TC − 3.8 46.2 — 37.9 — ns 178 CAS deassertion to WR5 assertion tRCH 1.75 × TC − 3.7 13.8 — 10.9 — ns 179 RAS deassertion to WR5 assertion tRRH 0.25 × TC − 2.0 0.5 — 0.1 — ns 180 CAS assertion to WR deassertion tWCH 6 × TC − 4.2 55.8 — 45.8 — ns 181 RAS assertion to WR deassertion tWCR 9.5 × TC − 4.2 90.8 — 75.0 — ns 182 WR assertion pulse width tWP 15.5 × TC − 4.5 150.5 — 124.7 — ns 183 WR assertion to RAS deassertion tRWL 15.75 × TC − 4.3 153.2 — 126.9 — ns 184 WR assertion to CAS deassertion tCWL 14.25 × TC − 4.3 138.2 — 114.4 — ns 185 Data valid to CAS assertion (write) tDS 8.75 × TC − 4.0 83.5 — 68.9 — ns 186 CAS assertion to data not valid (write) tDH 6.25 × TC − 4.0 58.5 — 48.1 — ns 187 RAS assertion to data not valid (write) tDHR 9.75 × TC − 4.0 93.5 — 77.2 — ns 188 WR assertion to CAS assertion tWCS 9.5 × TC − 4.3 90.7 — 74.9 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × TC − 4.0 11.0 — 8.5 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 4.75 × TC − 4.0 43.5 — 35.6 — ns 191 RD assertion to RAS deassertion tROH 15.5 × TC − 4.0 151.0 — 125.2 — ns 192 RD assertion to data valid tGA 14 × TC − 5.7 — 134.3 — 111.0 ns 193 RD deassertion to data not valid3 tGZ 0.0 — 0.0 — ns 194 WR assertion to data active 0.75 × TC − 0.3 7.2 — 5.9 — ns 195 WR deassertion to data high impedance 0.25 × TC —2.5 —2.1 ns Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 (Continued) No. Characteristics3 Symbol Expression 100 MHz 120 MHz Unit Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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