DSP56362AD datasheet(45/168 Pages) MOTOROLA

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Specifications

EXTERNAL CLOCK OPERATION

MOTOROLA

DSP56362 Advance Information

2-7

• With PLL enabled (42.5%–57.5% duty

cycle6)

4.25 ns 157.0

µs 4.25 ns 1570.00

EXTAL cycle time2

ETC

• With PLL disabled

10.00 ns

∞

8.33 ns

—

• With PLL enabled

10.00 ns 273.1

µs 8.33 ns 273.1 µs

CLKOUT change from EXTAL fall with PLL

disabled

4.3 ns

11.0 ns

CLKOUT rising edge from EXTAL rising

edge with PLL enabled (MF = 1,

PDF = 1, Ef > 15 MHz)3,5

0.0 ns

1.8 ns

CLKOUT falling edge from EXTAL rising

edge with PLL enabled (MF = 2 or 4, PDF =

1, Ef > 15 MHz)3,5

0.0 ns

1.8 ns

CLKOUT falling edge from EXTAL falling

edge with PLL enabled (MF

≤ 4, PDF ≠ 1,

Ef / PDF > 15 MHz)3,5

0.0 ns

1.8 ns

Instruction cycle time = ICYC = TC

See Table 2-5 (46.7%–53.3% duty cycle)

ICYC

• With PLL disabled

0.00 ns

∞

• With PLL enabled

0.00 ns 8.53

µs

8.53

µs

Notes:

Measured at 50% of the input transition

The maximum value for PLL enabled is given for minimum VCO and

maximum MF.

Periodically sampled and not 100% tested

The maximum value for PLL enabled is given for minimum VCO and

maximum DF.

The skew is not guaranteed for any other MF value.

The indicated duty cycle is for the specified maximum frequency for which

a part is rated. The minimum clock high or low time required for correction

operation, however, remains the same at lower operating frequencies;

therefore, when a lower clock frequency is used, the signal symmetry may

vary from the specified duty cycle as long as the minimum high time and

low time requirements are met.

Table 2-5 Clock Operation (Continued) 100 and 120 MHz Values

No.

Characteristics

Symbol

100 MHz

120 MHz

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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