DSP56362AD datasheet(72/168 Pages) MOTOROLA

72 / 168 page

2-34

DSP56362 Advance Information

MOTOROLA

Specifications

External Memory Expansion Port (Port A)

182 WR assertion pulse width

tWP

4.5

× TC − 4.5

220.5

—

145.5

—

183 WR assertion to RAS

deassertion

tRWL

4.75

× TC − 4.3 233.2

—

154.0

—

184 WR assertion to CAS

deassertion

tCWL

4.25

× TC − 4.3 208.2

—

137.4

—

185 Data valid to CAS

assertion (write)

tDS

2.25

× TC − 4.0 108.5

—

71.0

—

186 CAS assertion to data not

valid (write)

tDH

1.75

× TC − 4.0

83.5

—

54.3

—

187 RAS assertion to data not

valid (write)

tDHR

3.25

× TC − 4.0 158.5

—

104.3

—

188 WR assertion to CAS

assertion

tWCS

× TC − 4.3

145.7

—

95.7

—

189 CAS assertion to RAS

assertion (refresh)

tCSR

0.5

× TC − 4.0

21.0

—

12.7

—

190 RAS deassertion to CAS

assertion (refresh)

tRPC

1.25

× TC − 4.0

58.5

—

37.7

—

191 RD assertion to RAS

deassertion

tROH

4.5

× TC − 4.0

221.0

—

146.0

—

192 RD assertion to data valid

tGA

× TC − 7.5

—

192.5

—

125.8

193 RD deassertion to data

not valid3

tGZ

0.0

—

0.0

—

194 WR assertion to data

active

0.75

× TC − 0.3

37.2

—

24.7

—

195 WR deassertion to data

high impedance

0.25

× TC

—

12.5

—

8.3

Notes: 1.

The number of wait states for out of page access is specified in the DCR.

The refresh period is specified in the DCR.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and

not tGZ.

Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states. See

Figure 2-16.

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued)

No.

Characteristics3

Symbol

Expression

20 MHz4

30 MHz4

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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