STA1295 datasheet(52/109 Pages) STMICROELECTRONICS

52 / 109 page

Package pinouts and signal description

STA1295, STA1275

52/109

DS12586 Rev 5

FSMC_SMADQ_3

GPIO96

E10

I/O

VIO

FSMC. Multiplexed address/data line

FSMC_OEn

GPIO103

E11

VIO

FSMC. Output enable signal (active

low).

SQI_SCK

GPIO112

C14

VIO

SQI. Clock line.

SQI_SIO0

GPIO111

B14

I/O

VIO

SQI. Data line 0.

SQI_SIO1

GPIO110

B15

I/O

VIO

SQI. Data line 1.

SQI_SIO2

GPIO109

C12

I/O

VIO

SQI. Data line 2.

SQI_SIO3

GPIO108

E13

I/O

VIO

SQI. Data line 3.

FSMC_BUSYn

GPIO102

D11

VIO

FSMC Busy.

Busy signal for NAND flash memory

(active low). It needs an external PU.

FSMC_ADVn

GPIO85

AA14

VIO

FSMC Address Valid. When low

indicates address valid on SMADQ

bus.

FSMC_WEn

GPIO104

D12

VIO

FSMC Write Enable.

For SRAM/NOR-Flash and NAND-

Flash (active low).

DDR_DQ31

—

I/O

DDR_VIO Data line 31

DDR_DQ30

—

AA8

I/O

DDR_VIO Data line 30

DDR_DQ29

—

I/O

DDR_VIO Data line 29

DDR_DQ28

—

AB8

I/O

DDR_VIO Data line 28

DDR_DQ27

—

I/O

DDR_VIO Data line 27

DDR_DQ26

—

I/O

DDR_VIO Data line 26

DDR_DQ25

—

AA6

I/O

DDR_VIO Data line 25

DDR_DQ24

—

AB6

I/O

DDR_VIO Data line 24

DDR_DQ23

—

Y11

I/O

DDR_VIO Data line 23

DDR_DQ22

—

AA11

I/O

DDR_VIO Data line 22

DDR_DQ21

—

AB11

I/O

DDR_VIO Data line 21

DDR_DQ20

—

W10

I/O

DDR_VIO Data line 20

DDR_DQ19

—

I/O

DDR_VIO Data line 19

DDR_DQ18

—

I/O

DDR_VIO Data line 18

DDR_DQ17

—

AA9

I/O

DDR_VIO Data line 17

DDR_DQ16

—

AB9

I/O

DDR_VIO Data line 16

DDR_DQ15

—

I/O

DDR_VIO Data line 15

DDR_DQ14

—

I/O

DDR_VIO Data line 14

DDR_DQ13

—

I/O

DDR_VIO Data line 13

Table 26. Memory signals (continued)

Name

GPIOs

BALLs DIR

Power

domain

Description

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