STA1295 datasheet(18/109 Pages) STMICROELECTRONICS

18 / 109 page

System description

STA1295, STA1275

18/109

DS12586 Rev 5

•

And a third DSP configured as:

–

8k x 32 bit program PRAM

–

32k x 24 bit data XRAM

–

16k x 24 bit data YRAM

Each DSP is connected to other DSPs and audio peripherals by means of a programmable

isochronous bus infrastructure which guarantees a controlled throughput and latency for all

audio transfers.

2.12

Ethernet MAC Controller

Connection to Ethernet infrastructure is supported by the ETH MAC, which can be

connected to an external PHY with either RGMII or RMII interfaces. Ethernet MAC also

implements AVB features, and is compatible with the following standards:

•

IEEE 1588-2008 for precision networked clock synchronization

•

IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic

•

RGMII/RTBI specification version 2.6 from HP/Marvell

•

RMII specification version 1.2 from RMII consortium

MAC controller has separate channels or queues for AV data transfer in 100 Mbps and

1000 Mbps modes with single Tx/Rx FIFOs for all selected queues.

2.13

System DMA

DMA is designed to efficiently perform memory to memory, and memory to peripherals

transfers, offloading such tasks from the processor, thus reducing interrupt handling load.

DMA provides 16 independent channels which can be dynamically assigned to different

data-path. Complex scatter/gather transfers can be implemented by programming specific

DMA command linked lists.

2.14

Secure CAN subsystem

STA1275 and STA1295 allow isolating critical code from main application by implementing a

dedicated subsystem based on ARM® Cortex® M3, along with:

•

256 KB dedicated embedded SRAM

•

Interrupt controller

•

Timers

•

CAN controller, implementing CAN (CAN0) and FD-CAN (CAN1 and CAN2)

•

Dedicated GPIOs

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Dedicated Wakeup lines

•

Back-up RAM in always on domain

•

Local RTC

•

Secure OTP, user programmable

All of the above can be completely isolated from the rest of the system. This subsystem can

be dedicated to implement secure features, such as boot authentication, as well as interrupt

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