STA1295 datasheet(7/109 Pages) STMICROELECTRONICS

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DS12586 Rev 5

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STA1295, STA1275

System description

106

System description

2.1

Application processor

STA1275 and STA1295 processing capability relies on an ARM® Cortex® A7 (single or dual,

according to the versions) running at up to 650 MHz, delivering 2500+ DMIPS with minimal

heat dissipation requirements. The application processor has 32 KB of instruction cache

and 32 KB of data cache, as well as 256 KB of L2 cache for high throughput and low latency

tasks. The Cortex® A7 core implementation is equipped with a dedicated PLL and power

domain, in order to achieve best thermal/MIPS performance compromise in all application

scenarios.

The application processor is connected to the system via an efficient bus matrix

infrastructure, implementing flexible QoS and trust zone features.

2.2

Memory architecture

2.2.1

Embedded memory

STA1275 and STA1295 embed 768 KB of 64 bits SRAM memory clocked at 200 MHz,

which can be used for secure data storage.The whole embedded memory is also cacheable

and can be accessed by DMA.

2.2.2

DDR controller

DDR controller supports DDR3L JEDEC interface 16 or 32 bits wide (depending on the

versions), clocked at up to 660 MHz, allowing an optimal solution for throughput intensive

applications.

Such memory is cacheable, and can be accessed by DMA, and is flexibly configurable as

secure/non-secure.

2.2.3

SQI NOR interface

The SQIO controller allows interfacing Serial Quad I/O flash memories up to 125 MHz

(SDR).

Main features are:

•

Direct flash memory access

•

Fast memory access through page buffer (256 bytes)

•

Programmable single or quad I/O flash interface

SQI memory space can be partitioned in order to reserve a portion of the NOR device to the

Secure CAN Subsystem.

2.2.4

Parallel memory interface

FSMC static memory controller provides a generic 16-bits parallel interface suitable to

connect SRAM and NAND devices. This peripheral allows execution in-place from SRAMs,

as well as DMA accesses. Such interface can be used to store boot code into NAND.

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