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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA1295 데이터시트(PDF) 100 Page - STMicroelectronics |
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STA1295 데이터시트(HTML) 100 Page - STMicroelectronics |
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100 / 109 page  Electrical characteristics STA1295, STA1275 100/109 DS12586 Rev 5 4.14.7 Ethernet interface timing The following tables provide the timings for the Ethernet interface. In RGMII mode 1Gbit/sec speed, operation is double-data-rate. In all other modes, the active clock edge (data launch and data capture) is the rising clock edge. Timings are provided taking the active edges at SoC side as reference. Table 66. RGMII mode - 1Gbit/sec operation Type Symbol Min Max Unit Load Notes Clock CLK freq — 125 MHz 10 pF — CLK period 8 — ns 10 pF CLK duty cycle 45 55 % — Input TIS 1 — ns — TIH 1 — ns — Output Todly -0.5 0.5 ns 10 pF Data is launched in double data rate (on both of the clock edges) Table 67. RGMII mode - 100Mbit/sec operation Type Symbol Min Max Unit Load Notes Clock CLK freq — 25 MHz 10 pF — CLK period 40 — ns 10 pF CLK duty cycle 40 60 % — Input TIS 1 — ns — TIH 1 — ns — Output Todly -0.5 0.5 ns 10 pF Table 68. RGMII mode - 10Mbit/sec operation Type Symbol Min Max Unit Load Notes Clock CLK freq — 2.5 MHz 10 pF — CLK period 400 — ns 10 pF CLK duty cycle 40 60 % — Input TIS 1 — ns — TIH 1 — ns — Output Todly -0.5 0.5 ns 10 pF |
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