STA1295 datasheet(99/109 Pages) STMICROELECTRONICS

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DS12586 Rev 5

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STA1295, STA1275

Electrical characteristics

106

The capturing edge is programmable and should be chosen to be the one opposite to the

launching edge of external device.

Timings are provided taking the active edge at SoC side as reference.

4.14.6

SPI interface timing

The following tables provide the timings for SSP interface.

The clock and data alignment is configurable depending on the frame format that is

selected; data is assumed to always be captured on the clock edge opposite to the

launching edge.

Timings are provided taking the active edges (capture edge for inputs and launching edge

for outputs) at SoC side as reference.

Table 63. VIP timing

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

MHz

—

CLK period

16.7

—

CLK duty cycle

—

Input

TIS

—

TIH

0.5

—

Table 64. SSP - SPI (master)

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

MHz 25 pF

—

CLK period

19.2

—

25 pF

CLK duty cycle

—

Input

TIS

—

TIH

—

Output Todly

-2

25 pF

Table 65. SSP- SPI (slave)

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

MHz 25 pF

—

CLK period

83.3

—

25 pF

CLK duty cycle

—

Input

TIS

—

TIH

—

Output Todly

25 pF

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