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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA1295 데이터시트(PDF) 98 Page - STMicroelectronics |
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STA1295 데이터시트(HTML) 98 Page - STMicroelectronics |
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98 / 109 page  Electrical characteristics STA1295, STA1275 98/109 DS12586 Rev 5 4.14.4 LCD interface timing The following tables provide the timings for LCD interface. The launching edge is programmable: the edge should be chosen in such a way that capturing occurs on the clock edge opposite to the launching edge. Timings are provided taking the active edge at SoC side as reference. 4.14.5 VIP interface timing The following table provides the timings for VIP interface. Table 60. SQIO Type Symbol Min Max Unit Load Notes Clock CLK freq — 125 MHz 25 pF — CLK period 8 — ns 25 pF CLK duty cycle 40 60 % — Input TIS 0 — ns — TIH 2 — ns — Output Todly -1 1 ns 25 pF Table 61. LCD - Single display Type Symbol Min Max Unit Load Notes Clock Display CLK freq — 156 MHz 25 pF — Display CLK period 6.41 — ns 25 pF Display CLK duty cycle 40 60 % — Pixel CLK freq — 156 MHz 25 pF Pixel CLK period 6.41 — ns 25 pF Pixel CLK duty cycle 40 60 % — Output Todly -0.72 1 ns 25 pF Table 62. LCD - Dual display with edge shift (valid for each display output) Type Symbol Min Max Unit Load Notes Clock Display CLK freq — 44.55 MHz 25 pF — Display CLK period 22.45 — ns 25 pF Display CLK duty cycle 40 60 % — Pixel CLK freq — 89.1 MHz 25 pF Pixel CLK period 11.22 — ns 25 pF Pixel CLK duty cycle 40 60 % — Output Todly -2.5 3.5 ns 25 pF |
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