STA1295 datasheet(97/109 Pages) STMICROELECTRONICS

97 / 109 page

DS12586 Rev 5

97/109

STA1295, STA1275

Electrical characteristics

106

4.14.2

SDMMC1/2 interface timing

The following tables provide the timings for SDMMC1/2 interface.

Launching and capturing clock edges are as per standard. This means: in Default Speed

mode, launching occurs on falling clock edges and capturing occurs on rising clock edges.

In High Speed mode, launching and capturing both occur on rising clock edges.

Timings are provided taking the active edge at SoC side as reference.

4.14.3

SQIO interface timing

The following table provides the timings for SQIO interface.

Launching occurs on falling clock edge, capturing occurs on rising clock edge.

Timings are provided taking the active edge at SoC side as reference.

Table 58. Normal Speed (JEDEC); Default Speed (SD); UHS- I SDR12 (SD)

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

MHz 33 pF

IP can run up to 26 MHz. For SD modes, setting

of 24 MHz is recommended to meet typical

external component limitations (25 MHz).

CLK period

38.4

—

33 pF

—

CLK duty cycle

—

Input

TIS

—

6 ns in case internal clocking mode is used (no

feedback clock)

TIH

2.5

—

Output Todly

13.7

33 pF

Table 59. High Speed SDR (JEDEC); High Speed (SD); UHS- I SDR25 (SD)

Type

Symbol

Min Max Unit Load

Notes

Clock

CLK freq

—

MHz 33 pF

IP can run up to 52 MHz. Setting of 48 MHz is

recommended to meet typical external

component limitations (50 MHz).

CLK period

19.2

—

33 pF

—

CLK duty cycle

—

Input

TIS

—

TIH

2.5

—

Output Todly

2.2

33 pF

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