DSP56367 datasheet(31/100 Pages) FREESCALE

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Reset, Stop, Mode Select, and Interrupt Timing

DSP56367 Technical Data, Rev. 2.1

Freescale Semiconductor

3-7

3.9

Reset, Stop, Mode Select, and Interrupt Timing

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1

No.

Characteristics

Expression

Min

Max

Unit

Delay from RESET assertion to all pins at reset value2

—

26.0

Required RESET duration3

• Power on, external clock generator, PLL disabled

• Power on, external clock generator, PLL enabled

• Power on, Internal oscillator

• During STOP, XTAL disabled

• During STOP, XTAL enabled

• During normal operation

× ETC

1000

× ETC

75000

× ETC

75000

× ETC

2.5

× TC

2.5

× TC

333.4

6.7

500

16.7

—

µs

Delay from asynchronous RESET deassertion to first

external address output (internal reset deassertion)4

•Minimum

•Maximum

3.25

× TC + 2.0

20.25

× TC + 10

23.7

—

145.0

Syn reset setup time from RESET

•Maximum

—6.7

Syn reset deassert delay time

•Minimum

•Maximum

3.25

× TC + 1.0

20.25

× TC + 5.0

22.7

—

140.0

Mode select setup time

30.0

—

Mode select hold time

0.0

—

Minimum edge-triggered interrupt request assertion width

4.4

—

Minimum edge-triggered interrupt request deassertion width

4.4

—

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory access address out valid

• Caused by first interrupt instruction fetch

• Caused by first interrupt instruction execution

4.25

× TC + 2.0

7.25

× TC + 2.0

30.3

50.3

—

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first interrupt

instruction execution

× TC + 5.0

71.7

—

Delay from address output valid caused by first interrupt

instruction execute to interrupt request deassertion for level

sensitive fast interrupts5, 6, 7

(WS + 3.75)

× TC – 10.94

—

Note 8

Delay from RD assertion to interrupt request deassertion for

level sensitive fast interrupts5, 6, 7

(WS + 3.25)

× TC – 10.94

—

Note 8

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