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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56367 데이터시트(PDF) 47 Page - Freescale Semiconductor, Inc |
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DSP56367 데이터시트(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 100 page  External Memory Expansion Port (Port A) DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-23 191 RD assertion to RAS deassertion tROH 4.5 × TC − 4.0 221.0 — 146.0 — ns 192 RD assertion to data valid tGA 4 × TC − 7.5 — 192.5 — 125.8 ns 193 RD deassertion to data not valid4 tGZ 0.0 — 0.0 — ns 194 WR assertion to data active 0.75 × TC − 0.3 37.2 — 24.7 — ns 195 WR deassertion to data high impedance 0.25 × TC — 12.5 — 8.3 ns 1 The number of wait states for out of page access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (Figure 3-14). 4 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. Table 3-12 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2, 3 No. Characteristics Symbol Expression 100 MHz Unit Min Max 157 Random read or write cycle time tRC 12 × TC 120.0 — ns 158 RAS assertion to data valid (read) tRAC 6.25 × TC − 7.0 — 55.5 ns 159 CAS assertion to data valid (read) tCAC 3.75 × TC − 7.0 — 30.5 ns 160 Column address valid to data valid (read) tAA 4.5 × TC − 7.0 — 38.0 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 162 RAS deassertion to RAS assertion tRP 4.25 × TC − 4.0 38.5 — ns 163 RAS assertion pulse width tRAS 7.75 × TC − 4.0 73.5 — ns 164 CAS assertion to RAS deassertion tRSH 5.25 × TC − 4.0 48.5 — ns 165 RAS assertion to CAS deassertion tCSH 6.25 × TC − 4.0 58.5 — ns 166 CAS assertion pulse width tCAS 3.75 × TC − 4.0 33.5 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × TC ± 4.0 21.0 29.0 ns 168 RAS assertion to column address valid tRAD 1.75 × TC ± 4.0 13.5 21.5 ns 169 CAS deassertion to RAS assertion tCRP 5.75 × TC − 4.0 53.5 — ns 170 CAS deassertion pulse width tCP 4.25 × TC − 4.0 38.5 — ns 171 Row address valid to RAS assertion tASR 4.25 × TC − 4.0 38.5 — ns 172 RAS assertion to row address not valid tRAH 1.75 × TC − 4.0 13.5 — ns Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued) No. Characteristics Symbol Expression 20 MHz3 30 MHz3 Unit Min Max Min Max |
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