DSP56367 datasheet(63/100 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56367 Technical Data, Rev. 2.1

Freescale Semiconductor

3-39

Figure 3-27 SPI Master Timing (CPHA = 0)

160

SS deassertion pulse width (CPHA = 0)

Slave

—

TC + 6

12.7

—

161

HREQ in assertion to first SCK edge

Master

Bypassed

Narrow

Wide

0.5

× tSPICC + 2.5 × TC + 43

0.5

× tSPICC + 2.5 × TC + 43

0.5

× tSPICC + 2.5 × TC + 43

97.8

160.8

196.8

—

162

HREQ in deassertion to last SCK

sampling edge (HREQ in set-up time)

(CPHA = 1)

Master

—

163

First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

—

1 V

CC = 1.8 V ± 5%; TJ = –40°C to +95°C, CL = 50 pF

2 The timing values calculated are based on simulation data at 150MHz. Tester restrictions limit SHI testing to lower clock

frequencies.

3 Periodically sampled, not 100% tested

Table 3-16 Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics1

Mode

Filter

Mode

Expression2

Min

Max

Unit

(Input)

SCK (CPOL = 0)

(Output)

SCK (CPOL = 1)

(Output)

MISO

(Input)

Valid

MOSI

(Output)

MSB

Valid

LSB

MSB

LSB

HREQ

(Input)

141

142

143

144

141

144

143

142

148

149

148

152

153

163

161

AA0271

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