DSP56367 datasheet(56/100 Pages) FREESCALE

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Parallel Host Interface (HDI08) Timing

DSP56367 Technical Data, Rev. 2.1

3-32

Freescale Semiconductor

332

HCS assertion to output data valid

—

19.1

333

HCS hold time after data strobe deassertion9

—0.0

—

334

Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)

—

4.7

—

335

Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)

—

3.3

—

336

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data

strobe assertion9

•Read

• Write

—0

4.7

—

337

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe

deassertion9

—3.3

—

338

Delay from read data strobe deassertion to host request assertion for “Last

Data Register” read4, 5, 10

6.7

—

339

Delay from write data strobe deassertion to host request assertion for “Last

Data Register” write5, 8, 10

× TC

13.4

—

340

Delay from data strobe assertion to host request deassertion for “Last Data

—

19.1

341

Delay from data strobe assertion to host request deassertion for “Last Data

—

300.0

342

Delay from DMA HACK deassertion to HOREQ assertion

• For “Last Data Register” read5

• For “Last Data Register” write5

• For other cases

× TC + 19.1

1.5

× TC + 19.1

32.5

29.2

0.0

—

343

Delay from DMA HACK assertion to HOREQ deassertion

•HROD = 05

—

20.2

344

Delay from DMA HACK assertion to HOREQ deassertion for “Last Data

• HROD = 1, open drain Host Request5, 11

—

300.0

1 See Host Port Usage Considerations in the DSP56367 User’s Manual.

2 In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3 V

CC = 1.8 V ± 5%; TJ = –40°C to +95°C, CL = 50 pF

4 The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.

5 The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.

6 This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers

without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.

7 This timing is applicable only if two consecutive reads from one of these registers are executed.

8 The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

Table 3-15

Host Interface (HDI08) Timing1, 2, 3 (continued)

No.

Characteristics

Expression

150 MHz

Unit

Min

Max

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