DSP56367 datasheet(32/100 Pages) FREESCALE

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Reset, Stop, Mode Select, and Interrupt Timing

DSP56367 Technical Data, Rev. 2.1

3-8

Freescale Semiconductor

Delay from WR assertion to interrupt request deassertion for

level sensitive fast interrupts5, 6, 7

• DRAM for all WS

•SRAM WS = 1

• SRAM WS = 2, 3

•SRAM WS

≥ 4

(WS + 3.5)

× TC – 10.94

N/A

1.75

× TC – 4.0

2.75

× TC – 4.0

—

Note 8

Synchronous int setup time from IRQs NMI assertion to the

CLKOUT trans.

0.6

× TC – 0.1

3.9

—

Synch. int delay time from the CLKOUT trans2 to the first

external address out valid caused by first inst fetch

•Minimum

•Maximum

9.25

× TC + 1.0

24.75

× TC + 5.0

62.7

—

170.0

Duration for IRQA assertion to recover from Stop state

0.6

× TC − 0.1

3.9

—

Delay from IRQA assertion to fetch of first instruction (when

exiting Stop)2, 8

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No

Stop Delay)

PLC

× ETC × PDF + (128 K

− PLC/2) × TC

PLC

× ETC × PDF + (23.75

+/- 0.5)

× TC

(8.25

± 0.5) × TC

—

51.7

—

58.3

Duration of level sensitive IRQA assertion to ensure interrupt

service (when exiting Stop)2, 8

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

• PLL is active during Stop (PCTL Bit 17 = 1) (implies no

Stop delay)

PLC

× ETC × PDF + (128 K

− PLC/2) × TC

PLC

× ETC × PDF + (20.5

+/- 0.5)

× TC

5.5

× TC

—

36.7

—

Interrupt Requests Rate

• HDI08, ESAI, ESAI_1, SHI, DAX, Timer

•DMA

•IRQ, NMI (edge trigger)

•IRQ (level trigger)

12TC

8TC

12TC

—

80.0

53.0

80.0

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)

No.

Characteristics

Expression

Min

Max

Unit

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