DSP56367 datasheet(62/100 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56367 Technical Data, Rev. 2.1

3-38

Freescale Semiconductor

144

Serial clock rise/fall time

Master

Slave

—

2000

146

SS assertion to first SCK edge

CPHA = 0

Slave

Bypassed

Narrow

Wide

3.5

× TC + 15

38.5

—

CPHA = 1

Slave

Bypassed

Narrow

Wide

—

147

Last SCK edge to SS not asserted

Slave

Bypassed

Narrow

Wide

102

189

102

189

—

148

Data input valid to SCK edge (data input

set-up time)

Master/

Slave

Bypassed

Narrow

Wide

MAX{(20-TC), 0}

MAX{(40-TC), 0}

13.3

33.3

—

149

SCK last sampling edge to data input not

valid

Master/

Slave

Bypassed

Narrow

Wide

2.5

× TC + 10

2.5

× TC + 30

2.5

× TC + 50

26.8

46.8

66.8

—

150

SS assertion to data out active

Slave

—

151

SS deassertion to data high impedance3

Slave

—

152

SCK edge to data out valid (data out delay

time)

Master/

Slave

Bypassed

Narrow

Wide

× TC + 33

× TC + 123

× TC + 210

—

46.4

136.4

223.4

153

SCK edge to data out not valid (data out

hold time)

Master/

Slave

Bypassed

Narrow

Wide

TC + 5

TC + 55

TC + 106

11.7

61.7

112.7

—

154

SS assertion to data out valid (CPHA = 0)

Slave

—

TC + 33

—

39.7

157

First SCK sampling edge to HREQ output

deassertion

Slave

Bypassed

Narrow

Wide

2.5

× TC + 30

2.5

× TC + 120

2.5

× TC + 217

—

46.8

136.8

233.8

158

Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

Narrow

Wide

2.5

× TC + 30

2.5

× TC + 80

2.5

× TC + 136

46.8

96.8

152.8

—

159

SS deassertion to HREQ output not

deasserted (CPHA = 0)

Slave

—

2.5

× TC + 30

46.8

—

Table 3-16 Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics1

Mode

Filter

Mode

Expression2

Min

Max

Unit

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