DSP56367 datasheet(36/100 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56367 Technical Data, Rev. 2.1

3-12

Freescale Semiconductor

Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service

Figure 3-8 External Memory Access (DMA Source) Timing

3.10

External Memory Expansion Port (Port A)

3.10.1

SRAM Timing

Table 3-8 SRAM Read and Write Accesses

No.

Characteristics

Symbol

Expression1

150 MHz

Unit

Min

Max

100

Address valid and AA assertion pulse width

tRC, tWC (WS + 2) × TC − 4.0 [2 ≤ WS ≤ 7]

(WS + 3)

× TC − 4.0 [WS ≥ 8]

22.7

69.3

—

101

Address and AA valid to WR assertion

tAS

0.75

× TC − 2.0[2 ≤ WS ≤ 3]

1.25

× TC − 2.0[WS ≥ 4]

3.0

6.3

—

102

WR assertion pulse width

tWP

× TC − 4.0 [2 ≤ WS ≤ 3]

(WS

− 0.5) × TC − 4.0[WS ≥ 4]

9.3

19.3

—

103

WR deassertion to address not valid

tWR

1.25

× TC − 4.0[2 ≤ WS ≤ 7]

2.25

× TC − 4.0[WS ≥ 8]

4.3

11.0

—

IRQA

A0–A17

First IRQA Interrupt Instruction Fetch

AA0467

DMA Source Address

First Interrupt Instruction Execution

A0–A17

IRQA, IRQB,

IRQC, IRQD,

NMI

AA1104

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