DSP56367 datasheet(50/100 Pages) FREESCALE

50 / 100 page

External Memory Expansion Port (Port A)

DSP56367 Technical Data, Rev. 2.1

3-26

Freescale Semiconductor

183

WR assertion to RAS deassertion

tRWL

15.75

× TC − 4.3

153.2

—

184

WR assertion to CAS deassertion

tCWL

14.25

× TC − 4.3

138.2

—

185

Data valid to CAS assertion (write)

tDS

8.75

× TC − 4.0

83.5

—

186

CAS assertion to data not valid (write)

tDH

6.25

× TC − 4.0

58.5

—

187

RAS assertion to data not valid (write)

tDHR

9.75

× TC − 4.0

93.5

—

188

WR assertion to CAS assertion

tWCS

9.5

× TC − 4.3

90.7

—

189

CAS assertion to RAS assertion (refresh)

tCSR

1.5

× TC − 4.0

11.0

—

190

RAS deassertion to CAS assertion (refresh)

tRPC

4.75

× TC − 4.0

43.5

—

191

RD assertion to RAS deassertion

tROH

15.5

× TC − 4.0

151.0

—

192

RD assertion to data valid

tGA

× TC − 5.7

—

134.3

193

RD deassertion to data not valid5

tGZ

0.0

—

194

WR assertion to data active

0.75

× TC – 1.5

6.0

—

195

WR deassertion to data high impedance

0.25

× TC

—2.5

1 The number of wait states for an out-of-page access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 An expression is used to compute the maximum or minimum value listed (or both if the expression includes ±).

4 Either t

RCH or tRRH must be satisfied for read cycles.

5 RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (continued)

No.

Characteristics

Symbol

Expression3

100 MHz

Unit

Min

Max

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